`timescale 1ns / 1ns
`define PMAP_LEN 50
module top12();

	reg			clk;
	reg			rst;
	wire	[7:0]	indata;
	reg			invalid;
	wire	[7:0]	data_1_2;
	wire			valid_1_2;
	wire			msg_end_1_2;
	wire	[7:0]	data_2_3;
	wire			valid_2_3;
	wire  [`PMAP_LEN - 1:0] sel_2_3;
	wire	[3:0] field_counter_2_3;
	wire			msg_end_2_3;
	
	reg	[7:0] data	[0:100];
	integer		counter;


stage1 field_sender(
	.valid_0_1(invalid),
	.data_0_1(indata),
	.valid_1_2(valid_1_2),
	.data_1_2(data_1_2),
	.msg_end_1_2(msg_end_1_2),
	
	.clk(clk),
	.rst(rst)	//P RST
);

field_spliter field_spliter(
	.rst_n(~rst),
   .clk(clk),
   .valid_1_2(valid_1_2),
   .data_1_2(data_1_2),
   .msg_end_1_2(msg_end_1_2),
   .valid_2_3(valid_2_3),
   .data_2_3(data_2_3),
   .sel_2_3(sel_2_3),
   .field_counter_2_3(field_counter_2_3),
   .msg_end_2_3(msg_end_2_3)
);

	initial 
	begin
		clk		=	0;
		rst		=	1;
		invalid	=	0;
		counter	=	0;
		$readmemh("test_data.txt",data);
		#12	rst	=	0;
		
		#10	invalid = 1;
		
		
		
	end
	
	always #10	clk	=	~clk;

	always @(posedge clk)
	begin
		if((~rst)&invalid)
			counter	<=	counter + 1;
	end
	
	assign indata	=	data[counter];

endmodule
